1. Field of the Invention
Exemplary embodiments of the present invention relate to a low-power and all-digital phase interpolator (PI)-based clock and data recovery (CDR) architect.
2. Discussion of the Background
A phase-locked loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input reference signal. The PLL is an electronic circuit consisting of a variable frequency oscillator and a phase detector. The electronic circuit compares the phase of the input signal with the phase of the signal derived from its output oscillator and adjusts the frequency of its oscillator to keep the phases matched. The signal from the phase detector is used to control the oscillator in a feedback loop.
Frequency is the time derivative of phase. Keeping the input and output phase in lock step implies keeping the input and output frequencies in lock step. Consequently, the PLL can track an input frequency, or the PLL can generate a frequency that is a multiple of the input frequency. The former property is used for demodulation, and the latter property is used for indirect frequency synthesis.
A delay-locked loop (DLL) is a digital circuit similar to the PLL, with the main difference being the absence of an internal voltage-controlled oscillator, replaced by a delay line.
A DLL can be used to change the phase of a clock signal (a signal with a periodic waveform), usually to enhance the clock rise-to-data output valid timing characteristics of integrated circuits (such as DRAM devices). The DLLs can also be used for clock recovery (CDR). From the outside, the DLL can be seen as a negative-delay gate placed in the clock path of a digital circuit.